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Zynqgeek Blog


A great question was posted by maw41 on the forums today:

maw41 wanted to know if he could pull the signals for the Ethernet MAC within the Processing System (PS) of the Zynq-7000 AP SoC device, out through the Programmable Logic (PL).  The answer is yes!

I thought I would take this opportunity though to talk about how to move signals from the MIO pins (those that are dedicated to the MIO Bank) to the EMIO pins (those that are available to the PL).


How to understand Zynq Pins! WooHoo!

A good question came up on the forums today by user atkarapa asking about MIO pins on the Zynq-7000.  So let's take a little bit of time going through what pins map to where, and get familiar with the naming schema that Xilinx uses for it's pins.

Last week Xilinx released the newest version of their tools, revisioned at 2012.3 (14.3).  I thought I would take a few minutes here to discuss a few things about Xilinx's tools, and how they are versioned.


Get to know the players

First let's get some nomenclature down:



ISE has been the primary Integrated Development Environment (IDE) for Xilinx for several years.  It is has been the primary launch point for all Real Time Logic (RTL) based projects



Hello There!
Well if you've found yourself here, then the move to the site was successful!  The nice folks over at Avnet were awesome enough to give me some website on the website, and well, here I am!

Check back soon for more blog posts!

I had a few questions about Warnings so I thought I would post a hopefully concise answer here.

Often it is the case that you will be designing hardware in either VHDL, Verilog, or Schematic Capture and when synthesizing that design you will receive a series of warnings.

First, it is always important to read through all messages that the tools provide, as it will both give you a better understanding of the tools as well as what they are doing.  This will lead to a better functional understanding of how your design is behaving both in simulation and in live silicon.

This is the second in the series of a Deep Dive into the Xilinx tool called PlanAhead.  Check out part 1 here.

So you want to be a hardware designer hu?  Cool.  Well we better get started right away!

This is the first of a series of posts that hope to better explain the PlanAhead software and some of it's features.  I have broken it up into different parts so it flows a bit nicer.  I will link the other posts here once I complete them.

So I wanted to touch on a really powerful tool that I have mentioned before, but haven't dove far into - the QEMU build that Xilinx provides for ARM development on Zynq.

I touched on how to download, and build QEMU previously, but I didn't touch on much more than that.

Note:  I am using Ubuntu 12.04 LTS for this blog post.

Over 10K page views! Woohoo!

Thanks everyone for the great feed back, and asking tough questions.  I am working on a series of how-to's that are deep dives for custom peripherals, as well as the one how-to that *everybody* wants - talking to a custom peripheral via Linux (it's a bit harder then I expected lol).

New posts coming soon!  Thanks again everyone!

I know a lot of you have been waiting for this: we're going to create a custom peripheral in the Programmable Logic (PL) portion of the Zynq-7000 device, and talk to it via one of the ARM cores! woohoo!

The github project can be found here.  Enjoy!

Again, as previous posts, I am using the Avnet Zedboard - because it's awesome (and because I don't have a ZC702 board yet).